This invention relates generally to semiconductor memory devices and more particularly, it relates to a BICMOS (Bipolar/CMOS mixed type) read/write control and sensing circuit for MOS-type memory cells in which data can be written into and sensed in the memory cells at high speeds without reducing its stability.
Conventional read/write control and sensing circuits for MOS-type memory cells employing only MOS (metal-oxide semiconductor) transistors are generally well known in the art. Typically, a plurality of asymmetrical memory cells are arranged in an array forming columns of bits and rows of words where each memory cell is disposed for storing and retrieving binary information. Each memory cell may be comprised of a MOS cross-coupled latch and a pair of coupling transistors coupled between the latch and a pair of bit lines, which are used as a means for both writing information into the memory cell and sensing (reading) information from the memory cell.
Since the pair of bit lines are relatively long conductors which have coupled therebetween a number of memory cells, they represent a relatively large capacitive load. These MOS latches are ordinarily not capable of providing a high current so as to charge up or discharge rapidly the capacitive load of the bit lines. As a result, these prior art read/writes control and sensing circuits suffered from the disadvantages of increased write and read times to and from the memory cells.
It would therefore be desirable to provide a merged or composite bipolar/CMOS read/write control and sensing circuit which has the advantages of high writing speeds and high reading speeds. The read/write control and sensing circuit of the present invention is achieved by combining the bipolar transistor and CMOS transistor technologies together. As a result, bipolar transistors and CMOS transistors are merged or are arranged in a common semiconductor substrate in order to form an integrated circuit read/write control and sensing circuit of the present invention.